一种提高SRAM写能力的自适应负位线电路设计

An Adaptive Negative Bit-Line Voltage Scheme for Improving Write-Ability of SRAM

随着器件尺寸缩小到纳米级,在SRAM生产过程中,工艺偏差变大会导致SRAM单元写能力变差.针对这一问题,提出了一种新型负位线电路,可以提高SRAM单元的写能力,并通过控制时序和下拉管的栅极电压达到自我调节负位线电压,使负电压被控制在一定范围内.本设计采用TSMC 40nm工艺模型对设计的电路进行仿真验证,结果证明,设计的电路可以改善写能力,使SRAM在电压降到0.66V的时候仍能正常工作,并且和传统设计相比,本电路产生的负电压被控制在一个范围内,有利于提高晶体管的使用寿命,改善良率,节省功耗.

With the feature size falling into nano-scale ,the increased process variation degrades write-ability of SRAM cells in the process of producing SRAM .To solve this problem ,a novel negative bit-Line voltage scheme is presented to improve write-ability of SRAM cell . With controlling timing and the gate voltage of pull-down transistor ,the negative voltage can be self-adjusted and suppressed in a certain range .The result is verified by using TSMC 40 nm process model .The result shows that the write-ability can be improved by the newly designed circuit . SRAM even can operate normally at 0 .66 V .As the voltage increase ,the negative voltage is suppressed in a certain range ,which can improve the using life of transistors and the product yields .