5.8GHz堆叠式功率放大器设计

Design of a 5.8GHz Stacked Power Amplifier

基于2μm GaAs HBT工艺,采用堆叠晶体管结构设计了一款5.8GHz功率放大器。通常堆叠式功率放大器在高频情况下,上下两层晶体管间需要电感来完成功率匹配,在芯片设计中其电感会增加版图面积和级间功耗,为此该设计则利用上层晶体管的基极与地之间的串联电阻、电容等效成堆叠结构级间的感性负载,从而减小了级间的损耗与匹配难度。实测结果表明,该堆叠功率放大器在5.8GHz时增益为20.6dB,饱和输出功率为29dBm,饱和输出时功率附加效率达到36.4%,芯片面积仅为1×0.85mm2。

A 5.8GHz power amplifier （PA） using 2 μm GaAs HBT is developed. The proposed PA is designed based on a stacked circuit topology. At high frequency, the optimum impedance of the bottom transistors is not purely resistive, but has some inductive. This inter-stage inductor would increase the layout area and bring some ohmic loss. In this design, this optimum impedance is achieved by adjusting the series resistance and capacitance between the base of the upper transistors and the ground. The measurement results of the PA exhibits the small signal gain higher than 20.6dB, and the saturation output power higher than 29dBm with a power added efficiency of 36.4% at 5.8GHz. The chip size is 1 ×0. 85 mm^2.