低功耗UHFRFID射频/模拟前端解决方案

Low power RF/analog front-end solution for UHF RFID

提出了用于无源超高频射频识别(UHF RFID)芯片的射频/模拟前端.该射频/模拟前端通过系统分区和分时供电优化了系统功耗,子电路包括整流电路、基准电路、三轨稳压电路、解调/调制电路、上电复位电路以及时钟电路.通过引入阈值补偿,将全CMOS整流电路的整流效率提升至不低于48%;电流求和型亚阈值基准电路在保证基准精度的同时,有效降低了功耗和芯片面积;无需大尺寸无源器件的解调电路,并从系统架构层面解决了解调失真的问题.该射频/模拟前端电路采用SMIC 0.18μm CMOS工艺库仿真并投片验证,测试结果表明:直流功耗为3.6μA,芯片有效面积为0.27mm2.将该射频/模拟前端电路集成至一款UHF RFID标签芯片中,采用商用阅读器进行测试,其读取距离>6m,平均读取速率达到89.9个/s.

A RF/analog front-end for passive UHF RFID was presented.The system power consumption was optimized by time-divided and domain-divide power supply.The overall circuits included voltage multiplier,three voltage regulators,power-on-reset,ring oscillator,voltage reference,modulator and demodulator,where the power efficiency voltage multiplier was improved through threshold voltage compensation,and the power efficiency was not smaller than 48%;the low power current-summing voltage reference had both high accuracy and small chip size;the amplitude shift keying（ASK）demodulator without huge passive devices solved the error-detection and distortion problem through system level.The RF/analog front-end was designed and implemented in SMIC 0.18μm CMOS technology.Test results show that the total direct current（DC）power consumption is 3.6μA.The active area of the RF/analog front-end is about 0.27mm2.The RF/analog front-end was finally integrated into a full UHF RFID chip,and tested by a commercial reader.The reading distance is larger than 6m,and the read speed of the RFID chip reaches 89.9/s.