具有部分n^+浮空埋层的高压SJ-LDMOS器件新结构

A new high-voltage SJ-LDMOS with partial n^+-floating layer

为了抑制衬底辅助耗尽(SAD)效应并提高超结器件击穿电压,提出一种具有部分n+浮空层SJ-LDMOS新结构。n+浮空等位埋层能够调制器件横向电场,使得partial n+-floating SJ-LDMOS比传统SJ-LDMOS具有更加均匀的电场分布。通过三维仿真软件对新器件结构分析,与传统SJ-LDMOS进行比较。仿真结果表明,具有部分n+浮空层SJ-LDMOS结构的器件能将器件的击穿电压从138V提高到302V,且比导通电阻也从33.6mΩ·cm2降低到11.6mΩ·cm2,获得一个较为理想的低导通电阻高压功率器件。

In order to suppress the substrate-assisted depleted（SAD）effect and obtain high breakdown voltage in the super junction device,a new high-voltage SJ-LDMOS with partial n^＋-floating layer is introduced.The electric field is more uniformity distribution in the partial n^＋-floating SJ-LDMOS than those in the conventional SJ-LDMOS,which causes n^＋-floating equipotential buried layer to redistribute the bulk electric field.The proposed SJ-LDMOS transistor with partial n^＋-floating layer is analyzed and compared with the conventional SJ-LDMOS by 3Dnumerical simulations.The results indicate that the proposed structure can significantly improve breakdown voltage from 138 Vup to 302 Vand reduce on-resistance from16.8mΩ·cm2 down to 5.8mΩ·cm^2.A relative ideal low on-resistance high-voltage power device is obtained.