基于一款EEPROM IP核的读写控制设计

Based on block an EEPROM IP core of reading and writing control design

对于芯片处理的数据可以在其内部存储,同时又为了简化芯片的设计,可在芯片内部嵌入存储器IP核。本文设计了华虹一款EEPROM IP核的读写时序,采用Verilog语言描述,并在Model Sim SE的环境下进行仿真,实现了数据的读写。

Data for the chip processing in its internal storage, at the same time,in order to simplify the design of the chip, IP core can be embedded within the chip memory. This paper designs the huahong block an EEPROM read and write timing of IP core, using Verilog language description,and carries on the simulation under the environment of Model Sim SE, has realized the data read and write.