摘要
本文主要阐述了在深亚微米下面的逻辑综合的过程。对综合过程的主要的逻辑约束进行详细分析,并根据MCU芯片的结构特点,进行时钟的定义。同时,本文详细分析了时钟定义、电源、复位等问题的处理方法,最后达到时序收敛。再对满足时序的综合结果进行可测性设计,测试覆盖率达到99.5%。
The main logic constraints in integrated process have been analysed in detail, and the clock was defined according to the structural characteristics of MCU chip. Meanwhile, this paper analyzes the solutions including clock definition, power, reset, and other issues in detail, and finally reach timing closure. Meeting the timing of comprehensive results were designed for testability, the test coverage reached 99.5%.
出处
《中国集成电路》
2014年第10期52-55,共4页
China lntegrated Circuit
关键词
时序约束
时序收敛
测试覆盖率
timing constraints
timing closure
test coverage
