基于FPGA的1553B总线RT终端IP核设计

Design of 1553B RT IP Core based on FPGA

随着MIL-STD-1553B总线在航天和军工领域日益广泛应用,对其灵活性、可扩展性,低成本和小型化提出了更加苛刻的要求,传统的专用协议芯片实现方案已经不能完全满足需求.从新需求的角度出发,提出了一种以低成本FPGA为平台的1553B总线RT终端IP核方案,以片内逻辑实现1553B的全部RT终端协议.详细介绍了基于FPGA的1553B总线RT终端IP核硬件总体设计方案,IP核设计方法以及基于FPGA的1553B总线RT终端IP核的特性分析等.应用表明该终端节约了1553B总线的成本、降低功耗,提高了1553B的总线协议的效率.

With the application of MIL-STD-1553B bus is more and more widely in aerospace and military fields,it made more stringent requirements of low cost and miniaturization for its flexibility and scalability,therefore,implementation scheme of traditional special protocol chip can not meet the demand.From the angle of new demand,this paper presents a RT IP terminal scheme with low cost FPGA as the platform of the 1553B bus,and implements all of the RT terminal protocol to 1553B on-chip logic.It intruduces detailly 1553B bus RT IP terminal hardware design scheme based on FPGA and IP core design method,and based on the FPGA 1553B bus RT IP terminal characteristics analysis.Application shows that the terminal saves the cost of 1553B bus,reduces power consumption and improves the efficiency of the 1553B bus protocol.