隧穿电流影响下的小尺寸电路设计

Scaled Circuit Designed on Gate Tunneling Current

对于具有超薄的氧化层的小尺寸MOSFET器件,静态栅隧穿漏电流的存在严重地影响了器件的正常工作,基于新型应变硅材料所构成的MOSFET器件也存在同样的问题.为了说明漏电流对新型器件性能的影响,利用双重积分方法提出了小尺寸应变硅MOSFET栅隧穿电流理论预测模型,并在此基础上,基于BSIM4模型使用HSPICE仿真工具进行了仔细的研究,定量分析了在不同栅压、栅氧化层厚度下,MOSFET器件、CMOS电路的性能.仿真结果能很好地与理论分析相符合,这些理论和实验数据将有助于以后的集成电路设计.

For scaled MOSFET devices , normal operation of devices is seriously affected due to static gate tunneling leakage currents with ultra -thin gate oxide of MOSFET , and the new MOSFET devices based on strained Si .To illustrate the impacts of gate leakage current on performances of new devices , a theoretical gate tunneling currents predicting model was presented using double integral approach in this paper .On the basis of theoretical model , performances of MOSFET devices and CMOS circuit were quantitatively studied in detail using HSPICE simulator in BSIM4 model including different gate voltage and gate oxide thickness .The experiments show that simulation results well agree with theoretical analysis , and the theory and experimental data will con-tribute to future integrated circuit design .