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0.18 μm CMOS射频低噪声放大器设计 被引量:1

Design of 0.18 μm CMOS RF low-noise amplifier
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摘要 基于TSMC 0.18μm RFCMOS工艺,设计了一种工作于2.4 GHz频段的低噪声放大器。电路采用Cascode结构,为整个电路提供较高的增益,然后进行了阻抗匹配和噪声系数的性能分析,最后利用ADS2009对其进行了模拟优化。最后仿真结果显示。该放大器的正向功率增益为14 d B,噪声系数小于2 d B,1 d B压缩点为-13 d Bm,功耗为7.8 m W,具有良好的综合性能指标。 A 2.4 GHz low?noise amplifier(LNA)based on TSMC 0.18 μm RFCMOS technology is designed in this paper. A Cascode structure is adopted in the circuit,which leads to better gain for the circuit. The performance analyses of impedance matching and noise figure are conducted. ADS2009 is used for simulation and optimization of the amplifier. The simulation re?sults show that the LNA has a forward power gain of 14 dB,its noise figure is less than 2 dB,1 dB compression point is-13 dBm and the power consumption is 7.8 mW,and it has a better comprehensive performance.
出处 《现代电子技术》 2014年第24期98-100,104,共4页 Modern Electronics Technique
关键词 CMOS 低噪声放大器 噪声系数 阻抗匹配 CMOS low-noise amplifier noise figure impedance matching
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参考文献6

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