摘要
基于双线性内插算法,设计改进了一种以FPGA为硬件平台的多路视频信号的图像缩放装置。把与期望位置相邻的两行像素缓存在RAM中,先对垂直方向进行插值运算,再对水平方向进行插值运算。利用FPGA并行处理的优势实现多路视频信号的实时缩放。
A multi-channel video zoom device, which bases on bilinear interpolation algorithm and FPGA hardware platform, is de- signed in this paper. The two lines pixels, which are next to the desired position, are stored in the RAM. The vertical interpolation data are calculated firstly. Then, the horizontal interpolation data are calculated. The image can be scaled in real time by using this device, which takes advantage of FPGA＇ s parallel computation ability.
出处
《电视技术》
北大核心
2015年第1期43-46,共4页
Video Engineering
