基于FPGA的DDR3多端口读写存储管理设计

Multi-port Read-write Storage Management of DDR3 Based on FPGA

为了解决视频图形显示系统中多个端口访问DDR3时出现的数据存储冲突问题,设计了一种基于FPGA的DDR3存储管理系统。DDR3存储器控制模块使用MIG生成DDR3控制器,只需通过用户接口信号就能完成DDR3读写操作。DDR3用户接口仲裁控制模块将中断请求分成多个子请求,实现视频中断和图形中断的并行处理。帧地址控制模块确保当前输出帧输出的是最新写满的帧。验证结果表明,设计的DDR3存储管理系统降低了多端口读写DDR3的复杂度,提高了并行处理的速度。

In order to solve the problem of data storage conflicts of multi-port accessing DDR3 in the video and graphics display system, DDR3 storage management system based on FPGA is designed and implemented. MIG（Memory Interface Generator） is used to generate DDR3 controller in the DDR3 memory control module, so that the read and write operations can be done only through the user interface. The arbitration control module of DDR3 user interface turns interrupt request into multiple sub requests,then it can complete video and graphics interrupt parallel processing. Frame address control module makes sure that the output frame is the latest filled frame. The results show that the design of storage management system simplifies the complexity of multi-port to read and write DDR3 ,and the speed of parallel processing is improved.