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并发追踪数据流的多缓存选址算法

Multi-Buffer Location Selection Algorithm for Concurrent Trace Data Flows
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摘要 为了验证多核芯片的正确性,通常需要同时观测不同芯核上的多组信号.如何实时处理并发追踪中多组数据流已经成为多核芯片硅后功能验证所面临的关键挑战之一.本文提出了一种基于映射的自调节缓存选址(Map-Based Self-Regulation Location Selection,MSLS)算法,该算法通过优化多缓存选址,在片上网络通信带宽限制下保证了并发追踪数据流能够实时存储,同时降低了追踪数据流传输能耗.实验结果表明了该方法的有效性. With the development of multi-core processors,it becomes a key problem to transmit concurrent trace data simultaneously to on-chip buffer under bandwidth constraint. To deal with the problem,we propose a Map-based Self-regulation Location Selection（ MSLS） algorithm. This algorithm locates multiple trace buffers in interconnection fabrics under the bandwidth constraint,and reduces the average distance between trace sources and trace buffers. Experimental results show our algorithm can achieve high efficiency for post-silicon debug.
作者 高建良 李欣 王建新
机构地区 中南大学信息科学与工程学院
出处 《电子学报》 EI CAS CSCD 北大核心 2014年第11期2310-2313,共4页 Acta Electronica Sinica
基金 国家自然科学基金(No.61106036)
关键词 多核芯片 硅后调试 并发追踪 多缓存选址 片上网络 multi-core chip post-silicon debug concurrent trace multi-buffer location selection network-on-chip
分类号 TN911.23 [电子电信—通信与信息系统]
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参考文献13

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电子学报
2014年 第11期

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