图形处理器片段处理单元的设计与实现

Design and implementation of fragment operation unit in GPU

针对图形处理器三维引擎中对图形的后期处理需求,实现片段写入帧缓冲区前的测试、混合、逻辑操作、累积、清除和屏蔽等关键功能。分析并提取了Open GL核心库中的片段处理相关函数,确定了片段处理单元要实现的功能;合理安排多个片段处理功能的执行顺序,设计了基于流水线的片段处理单元结构;采用Verilog HDL对电路进行描述,采用Cadence NC-Verilog仿真工具进行虚拟验证,采用Xilinx的ISE工具进行综合,并在Xilinx Virtex6XC6VLX760 FPGA上进行原型验证,电路工作频率可以达到180 MHz,测试功能正确。在SMIC 65 nm CMOS工艺下,采用Synopsys Design-Compiler对设计进行综合,电路工作频率达到300 MHz,满足设计需求。

In view of the post-processing requirements of graphics on three-dimensional（ 3D） engine in Graphic Processing Unit（ GPU）, a series of key functions such as the test, blend, logic operation, accumulating, clear, mask are implemented before fragments are written into the frame buffer. The relative functions of fragment operation were analyzed and extracted from the Open GL core library, and then the realized functions of Fragment Operation Unit（ FOU） were confirmed.Based on reasonable arrangement of work orders for the different fragment operation functions, a unit structure for FOU was designed. Further, hardware circuit was described by Verilog HDL, and functional virtual verification was accomplished by Cadence NC-Verilog simulator. Finally, Xilinx ISE tools were used for comprehensive, and on Xilinx Virtex6 XC6VLX760 FPGA for prototype verification. As a result, the frequency of circuit operating was up to 180 MHz and the test functions were correct. In addition, the design was synthesized under SMIC 65 nm CMOS technology by Synopsys Design-Compiler. The frequency of FOU ASIC design was up to 300 MHz, which met the design requirements.