基于FPGA的K计数环路滤波器的设计

Design of the Count of K Loop Filter Based on FPGA

介绍了K计数环路滤波器的基本结构和工作原理,提出了一种基于FPGA的K计数环路滤波器的设计方法,采用Verilog硬件描述语言进行编程,Xilinx ISE软件进行综合及时序模拟。

This paper introduces the basic structure and working principle of the count of K loop filter,proposes a design method of the count of K loop filter based on FPGA,using Verilog hardware description language for designing,the Xilinx ISE software synthesis and timing simulation.