3Girau G, Martina M, Molino A, et al. FPGA digital down converter IP for SDR terminals[ C]//Proceeding of the Thirty - Sixth Asilomar Conference on Signals, Systems and Computers. Pacific Groove,USA:IEEE, 2002:1010- 1014.
4Jovanovie Dolecek, Mitra S K. Simple method for compensation of CIC decimation filter[ J]. Electronics Letters, 2008,44 (19) :1162- 1163.
5Carbonini L, Manara A. A procedure to evaluate the output VSWR of high power amplifier[ C ]//Proceeding of 1998 IEEE International Symposium on Electromagnetic Compatibility. Gaithersburg, USA: IEEE, 1998:241 - 244.