LDMOS器件软失效分析及优化设计

Soft Failure Analysis and Optimization of LDMOS Devices

横向扩散金属氧化物半导体(LDMOS)器件在高压静电放电(ESD)防护过程中易因软失效而降低ESD鲁棒性。基于0.25μm Bipolar-CMOS-DMOS工艺分析了LDMOS器件发生软失效的物理机理,并提出了增强ESD鲁棒性的版图优化方法。首先制备了含N型轻掺杂漏版图的LDMOS器件,传输线脉冲(TLP)测试表明,器件在ESD应力下触发后一旦回滞即发生软失效,漏电流从2.19×10-9 A缓慢增至7.70×10-8 A。接着,对LDMOS器件内部电流密度、空间电荷及电场的分布进行了仿真,通过对比发现电场诱导的体穿通是引起软失效及漏电流增大的主要原因。最后,用深注入的N阱替代N型轻掺杂漏版图制备了LDMOS器件,TLP测试和仿真结果均表明,抑制的体穿通能有效削弱软失效,使其适用于高压功率集成电路的ESD防护。

The electrostatic discharge （ESD） robustness of the lateral diffusion metal-oxide- semiconductor （LDMOS） devices can be weakened by the soft failure occurring in the high volt- age ESD protection process. In this paper, the physical mechanism of soft failure in the LDMOS devices fabricated using a 0.25μm Bipolar-CMOS-DMOS process is analyzed, and the LDMOS layout is optimized to improve the ESD robustness. Firstly, the LDMOS devices with an N type lightly doped drain （NLDD） layout are fabricated. The transmission line pulse （TLP） testing re- sults indicate that the soft failure occurs immediately once the LDMOS is triggered and shows the snapback, and the leakage current increases from 2.19×10^-9 A to 7.70×10^-8 A slowly. Then, the distributions of the internal current density, space charge and electric field in the LDMOS are studied by simulation. These results show that the soft failure and increased leakage current are mainly caused by the electric-field-induced bulk punch-through. Finally, the LDMOS layout is modified by using the deep injected N-well instead of the NLDD. Both the TLP testing and simu-lation results indicate that the soft failure of the optimized LDMOS can be effectively weakened as a result of suppressing bulk punch-through, providing a suitable ESD protection solution for high-voltage power integrated circuits.