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Energy Efficient On-Chip Communications Implementation Based on Power Slacks

Energy Efficient On-Chip Communications Implementation Based on Power Slacks
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摘要 The quest for energy efficiency has growing importance in high performance many-core systems. However, in current practices, the power slacks, which are the differences observed between the input power budget and the actual power consumed in the many-core systems, are typically ignored, thus leading to poor energy efficiency. In this paper, we propose a scheme to effectively power the on-chip communications by exploiting the available power slack that is totally wasted in current many-core systems. As so, the demand for extra energy from external power sources （e.g., batteries） is minimized, which helps improve the overall energy efficiency. In essence, the power slack is stored at each node and the proposed routing algorithm uses a dynamic programming network to find the globally optimal path, along which the total energy stored on the nodes is the maximum. Experimental results have confirmed that the proposed scheme, with low hardware overhead, can reduce latency and extra energy consumption by 44% and 48%, respectively, compared with the two competing routing methods. The quest for energy efficiency has growing importance in high performance many-core systems. However, in current practices, the power slacks, which are the differences observed between the input power budget and the actual power consumed in the many-core systems, are typically ignored, thus leading to poor energy efficiency. In this paper, we propose a scheme to effectively power the on-chip communications by exploiting the available power slack that is totally wasted in current many-core systems. As so, the demand for extra energy from external power sources （e.g., batteries） is minimized, which helps improve the overall energy efficiency. In essence, the power slack is stored at each node and the proposed routing algorithm uses a dynamic programming network to find the globally optimal path, along which the total energy stored on the nodes is the maximum. Experimental results have confirmed that the proposed scheme, with low hardware overhead, can reduce latency and extra energy consumption by 44% and 48%, respectively, compared with the two competing routing methods.
作者 Xiao-Yu Xia Wen-Ming Pan Jia-Chong Kan
机构地区 Guangzhou Institute of Advanced Technology Guangzhou Institute of Advanced Technology
出处 《Journal of Electronic Science and Technology》 CAS 2014年第4期354-360,共7页 电子科技学刊（英文版）
基金 supported by the National Natural Science Foundation of China under Grant No.61376024 and No.61306024 Natural Science Foundation of Guangdong Province under Grant No.S2013040014366 Basic Research Program of Shenzhen under Grant No.JCYJ20140417113430642 and No.JCYJ 20140901003939020
关键词 Adaptive routing dynamicprogramming network NETWORKS-ON-CHIP power slack. Adaptive routing, dynamicprogramming network, networks-on-chip, power slack.
分类号 TN86 [电子电信—信息与通信工程]
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参考文献16

  • 1C. Li, W. Zhang, C. B. Cho, and T. Li, "Solarcore: solar energy driven multi-core architecture power management," in Proc. of IEEE Int. Symposium on High Performance Computer Architecture, San Antonio, 20 II, pp. 205-216.
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Journal of Electronic Science and Technology
2014年 第4期

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