百万门系统级芯片的时钟树设计

Clock Tree Design Process for SoC

层次化设计是片上集成芯片开发采用的主流方法,它是一种自底向上的流程。但层次化设计也带来了时钟树设计难以掌握的问题。针对一款复杂So C系统芯片时钟树设计,详细分析了层次化时钟树综合需要解决的关键点,并提出有效的解决方案。实验表明该方案可以迅速实现时钟树收敛,提高设计效率。

Hierarchical design is a complex method adopted by the So C development, it is a bottom-up process, but the hierarchical design also brings the problem of the clock tree design. In the paper, analysis the clock tree design process in a complex So C system chip, detailed analysis the key difficulties of the hierarchical clock tree synthesis, and puts forward the effective solution. The experimental results show that the design scheme can quickly reach clock tree convergence and improve design efficiency.