摘要
以FPGA为硬件设计平台,实现AES数据加密记录器,重点讲述了AES算法的FPGA实现。利用MATLAB软件完成算法的密钥扩展及S盒设计,使其在硬件中的设计简化为查表操作;整体算法的设计采用流水线技术,提高了加密速度。同时,设计了汉明校验码解决由于NAND Flash位翻转经加密后带来的误码扩散的问题,将最后的纠错工作设计在计算机上完成,降低对硬件读数的影响,同时提高了系统的可靠性,该设计具有一定实用价值。
hnplemented with FPGA, the paper proposes a method to design data recorder with AES encryption, which is sim- plified with the encryption work partly done by MATLAB that is the key expansion and Subbyte box, and which is accelerated with Pipelining design. Also, Error-Check-Correct scheme is implemented in the system to resistance the error propagation problem and strengthen reliability. The final data correct work is finished on the PC to reduce its influence on the hardware reading speed.
出处
《电子技术应用》
北大核心
2015年第1期118-121,共4页
Application of Electronic Technique
基金
国家自然科学基金项目(51275491)
