基于数字电路的二阶Σ-Δ调制微加速度计

2nd-order Σ-Δ modulation micro-accelerometer based on digital circuit

为了简化模拟电路部分的设计,减少模拟电路的干扰,提出了一种基于数字电路的Σ-Δ调制微加速度计。在传统由纯模拟电路搭建的Σ-Δ接口电路基础上,将基于运算放大器的比例放大、微分、积分电路使用现场可编程门阵列(FPGA)进行实现。使用分立元件搭建了PCB板级电路,实现了采样频率为50 k Hz的二阶Σ-Δ闭环调制接口电路。测试结果表明:该加速度计灵敏度为1.4 V/gn,系统基带内闭环噪声密度小于400μgn/Hz1/2。

In order to simplify design of analog circuit and reduce interference of anolog circuit, a ∑-△ modulation micro-accelerometer based on digital circuit is presented. Field programmable gate array （FPGA） is used to implement the PID circuit based on structure of traditional ∑-△ interface circuit designed with pure analog circuit. PCB circuit is designed and a 2nd-order ∑-△ closed-loop interface with its sample frequency 50 kHz is built. Test results show that sensitivity of accelerometer is 1.4 V/gn, and the closed-loop noise density is less than 400 μgn/ Hz1/2.