摘要
为了使得待测信号,时间基准信号与实际计数闸门同步,消除对待测信号和时间基准信号产生的±1误差,采用改进的多周期同步频率测量,利用SOPC设计技术,以FPGA为核心,对标准脉冲信号计数,NiosⅡ软和处理器作为系统控制单元;并通过划分频率段,先粗测再精测,设置不同闸门时间,使得系统测量频率范围保证在0.1 Hz^10 MHz,兼顾了测量频率的精度,测量的高效率。
By using the SOPC design technology, an improved multi-period synchronous frequency was adopted in order to make the time reference signal and the actual count gate keep synchronous and eliminate the ± 1 errors that were generated by the time based signal and the signal to be measured. The FPGA was the core of the standard pulse count and the NioslI soft processor was used as the system control unit. By dividing the frequency band, setting different gate times and through first rough measure- ment and then precision measurement, it was ensured that the range of measurement frequency varied from O. 1 Hz to lOMHz It also satisfied the accuracy and the efficiency of the frequency measurement.
出处
《仪表技术与传感器》
CSCD
北大核心
2014年第12期56-58,共3页
Instrument Technique and Sensor