期刊文献+

一种提高安全计算机可靠性的内存检测设计 被引量:1

Design of memory detection for raising reliability of vital computer
下载PDF
导出
摘要 目前应用在嵌入式系统的各种内存检测方案,很难均衡地满足内存检测性能要求:比较高的检测覆盖率、比较低的硬件开销、比较高的检测速度。根据轨旁安全计算机的系统特性和安全性要求,提出了一种软硬件相结合的内存内建测试架构方案,利用硬件BIST方案来检测高层次内存故障和软件BIST方案来覆盖低层次内存故障。实际项目应用结果显示,该混合内存检测方案可以有效地减少硬件开销和降低检测时间,并提高内存故障检测覆盖率至99%,使系统能够满足高实时性、高安全性的要求。 Design scheme of memory detection applied to embedded devices currently,seemed difficult to meet three performances:high diagnostic coverage,low hardware cost and high testing speed.According to system property and safety requirement of track-side vital computer,the paper presented a design scheme of memory detection for safety device,combined hardware with software,used BIST hardware to detect high level memory fault,used BIST software to test low level fault.Experimental results showed that the hybrid memory detection methods could effectively detect memory failure and fault with high reliability requirement and high safety requirement,obtain a general increase in the diagnostic coverage to 99%,reduce hardware cost and testing time,meet the needs of highly real-time and high security.
出处 《铁路计算机应用》 2014年第10期47-52,共6页 Railway Computer Application
关键词 内存故障 安全 内存检测 memory fault safety memory detection
  • 相关文献

参考文献13

二级参考文献55

  • 1Ehsan Atoofian Zainalabedin Navabi.A Test Approach for Look-Up Table Based FPGAs[J].Journal of Computer Science & Technology,2006,21(1):141-146. 被引量:6
  • 2须自明,苏彦鹏,于宗光.基于March C-算法的SRAM BIST电路的设计[J].半导体技术,2007,32(3):245-247. 被引量:11
  • 3[1]The National Roadmap for Semiconductors.Semiconductor Industry Association,2000
  • 4[2]S Hamdioui,A J van de Goor.Experimental analysis of spot defects in SRAMs:Realistic fault models and tests.The 9th Asian Test Symp,Taipei,2000
  • 5[3]S Hamdioui,A J van de Goor,M Rodgers.March SS:A test for all static simple RAM faults.IEEE Int'l Workshop on Memory Technology,Design and Testing,Bendor,France,2002
  • 6[4]A J van de Goor,G N Gaydadjiev,V N Yarmolik,et al.March LR:A test for realistic linked faults.The 14th VLSI Test Symp,Princeton,NJ,1996
  • 7[5]A J van de Goor,Issam B S Tlili.A systematic method for modifying march tests for bit-oriented memories into tests for word-oriented memories.IEEE Trans on Computers,2003,52(10):1320-1331
  • 8[6]W L Wang,K J Lee,J F Wang.An on-chip march pattern generator for testing embedded memory cores.IEEE Trans on Very Large Scale Integration (VLSI) Systems,2001,9(5):730-735
  • 9[7]Dongkyu Youn,Taehyung Kim,Sungju Park.A microcode-based memory BIST implementing modified march algorithm.The 10th Asian Test Symp,Kyoto,Japan,2001
  • 10[8]A Benso,S Di Carlo,G Di Natale,et al.Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.Communications Magazine,2003,41(9):90-97

共引文献46

同被引文献5

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部