基于EDK的高速数据收发嵌入式用户IP核设计

Design of High-speed Data Transceiver Embedded User IP Core Based on EDK

介绍了基于FPGA嵌入式系统的多通道高速数据收发模块的用户IP核设计。在Xilinx公司的ISE开发工具中,用FPGA器件中的硬核Rocket IO及软核FIFO设计用户逻辑;使用嵌入式开发工具EDK封装成可在FPGA嵌入式系统中使用的用户自定义IP核,最后通过实际测试验证了该方法的实效性。

This paper introduces the user IP core design of multi-channel high-speed data transceiver module FPGA-based embedded systems. Of the Xilinx＇s ISE development tools,FPGA devices hardcore and soft-core FIFO RocketIO is used to design the user logic. The custom FPGA IP core used in embedded systems is packed using the embedded development tools of EDK. The effectiveness of the method is verified by actual test.