摘要
给出了GPS/BDS自动校时系统的设计方案,FPGA通过GPS/BDS授时接收机对接收到的时间信息进行处理,完成自动校时和计时功能.本系统的最大的优点是采用FPGA作为精确计时的控制芯片,采用GPS/BDS授时接收机作为高安全性、高可靠性的标准时钟源.
The paper proposes a designing plan of an automatic time-correction system of GPS/BDS. FPGA completes time-correction and timing function by processing the time information from the time transfer GPS/BDS receiver. The most remarkable advantage of the system is that it uses FPGA as precise timing control chip and uses the time transfer GPS/BDS receiver as high security and high reliability standard clock source.
出处
《湖南理工学院学报(自然科学版)》
CAS
2014年第4期68-70,共3页
Journal of Hunan Institute of Science and Technology(Natural Sciences)