基于FPGA的随机构造QC-LDPC分层译码器设计

Design on Randomly Constructed QC-LDPC Layered Decoder Based on FPGA

针对随机构造的QC-LDPC码可能在构造中产生会产生短环的情况,提出了添加约束使其没有短环的构造方法,对硬件实现中的采用分层译码算法进行了简要的介绍。实验仿真表明,与传统译码算法相比,分层译码算法具有效率高、延时短及吞吐量大等优点。选用Alter公司的EP3SL340H1152I4器件实现码长为4 096,列重为4,行重为16,码率为3/4的QC-LDPC码的硬件译码算法。译码器在100 MHz的工作频率下,最大迭代次数为5时,吞吐量可以达到157.05 Mbps。

For the case that randomly constructed QC-LDPC code may produce becate in structure,a construction method,which adds constraint to avoid becate,is proposed,and the application of layered decoding algorithm in hardware implementation is briefly introduced. The experimental simulation shows that compared with traditional decoding algorithm,the layered decoding algorithm has such advantages of high efficiency,short delay and large throughput. The whole design is synthesized under EP3SL340H1152I4 FPGA of Altera to implement QC-LDPC hardware decoding algorithm whose code length is 4096,column weight is 4,and row weight is 16. When the clock frequency is 100 MHz and the maximum iteration number is 5,the decoding throughput can be up to 157. 05 Mbps.