YHFT-XX芯片中长线延时优化策略

Delay optimization for long wire in YHFT-XX chip

结合YHFT-XX芯片中存在很多长路径的特点,对物理设计中长线的优化进行了研究,主要研究了三种中继器的插入对延时的影响,得出了不同长线下插入中继器的最优尺寸以及最优延时。结合具体的工程实践,运用得出的结论优化了长路径的延时。通过规整的中继器插入,将长线上中继器单元以及中继器单元间的间距进行优化,使得路径延时更小,通过跨模块的中继器插入优化,采用穿通技术,有效减小了延时,提升了芯片的时序性能。

Aiming at that there are many long paths in YHFT-XX chip,the optimization of long wires in physical design is studied.The effect of three kinds of repeater insertion is studied,and the optimal sizes of repeaters and delays of different long wires after repeater insertion are obtained.Combined with the concrete engineering practice,the obtained results are used to optimize the delay of long paths.Regular repeater insertion is used to optimize the repeaters and the gaps between repeaters for the sake of reducing the path delay.Feedthrough technique is used to optimize the repeater insertion across modules,thus effectively reducing the delay and improving the timing performance of the chip.