C程序的Verilog HDL实现

C program realized with Verilog HDL

随着电子信息技术的不断发展,电子系统模块化的设计思想已经深入人心。因此,加强软件和硬件模块设计经验的相互借鉴意义重大。针对这种情况,借助于有限状态机理论,提出了一种将C程序转化成Verilog HDL描述的具体方法。同时,详细介绍了有限状态机理论,分析了在利用有限状态机进行设计时应该遵循的准则,并给出了一个具体的转化实例和最终的仿真结果。从仿真结果可以看出此方法是可行的。

With the continuous development of electronic and information technology, the concept of electronic systems modular design has been known to people. Therefore, it is important to enhance the software and hardware modules design experience learning from each other. In this case, this study put forward a specific method to convert the C program into Verilog HDL with the help of the finite state machine theory to describe. Meanwhile, it introduces the theory of finite state machine in details, analyzes the rules should be followed when used with finite state machine in design, and then gives a examples of specific conversion and final simulation results. The simulation result shows that this method is feasible.