离散周期对伺服系统用全数字硬件化锁相环的影响机理

Effect of Discrete Period on All-Digital Full-Hardware Phase-Locked Loop Using in Servo System

基于FPGA/ASIC的全数字硬件化方案具有纯硬件性、高度并行性及全定制性等优点,是一种高速高性能的基于锁相环的磁编码器轴角转换单元设计方案。然而它却面临内部参数域确定及字长选取等问题,而上述问题与离散周期存在着紧密的联系。本文首先利用Delta算子对连续域的锁相环进行离散化,依据Delta域稳定性条件分析离散周期对锁相环的稳定性的影响机理,从而确定系数整数字长。然后通过建立误差源及误差传播路径L2范数模型,研究离散周期对改进结构锁相环的变量小数字长的影响规律,从而得到系统内部变量的小数字长设计的理论依据,最后的实验结果验证了分析的正确性。

The digital control system based on field-programmable gate array（FPGA） or application specific integrated circuits（ASIC） has the advantages of full-hardware,parallelism,and flexibility,so it is a high-speed,high-performance solution of magnetic encoder-to-digital converter（MEDC） with phaselocked loop（PLL）.But there are some problems such as determination of parameters-region,optimization of word-length etc,which have a close connection with discrete period.The delta operator is employed to discrete the continuous-time PLL system so as to do the stability analysis of discrete-time PLL system with one-step-delay firstly,so the integer word-length of coefficients are determined.And then,error source model and error propagations model based on L2-norm are established,and the effect of discrete period on fractional word-length of improved PLL is analysed,so the design method of fractional word-length is derived.The simulation and experimental results verify the correctness and effectiveness of proposed analysis.