摘要
ARINC659背板总线为综合化模块化航空电子(IMA)中在线可更换模块(LRM)之间数据传送的标准总线。多重冗余可重构的特性以及时间窗口触发的帧收发运行控制机制是ARINC659背板总线的突出特色,同时也使得基于ARINC659总线的系统测试变得更加复杂。采用SOPC技术构建基于FPGA的测试平台,32位高性能软核处理器NiosII作为控制核心和数据交换枢纽,W5300TCP/IP硬件协议栈实现测试平台中FPGA与上位机的通信。通过仿真实验,验证了该通信测试平台可以准确、可靠地实现所需功能。
ARINC659 bachplane bus is a standard bus of data transfer between the LineReplaceable Modulars（LRMs） in Integerated Avionics. The outstanding characteristics of ARINC659 backplane bus are multiple redundant reconfigurable and Frame transceiver operation control mechanism of time window trigger, Which , meanwhile, makes it＇s testing very complicated. This paper adopt the SOPC technology to build a test platform based on FPGA with 32-bit high performance soft core processor NioslI as hub of control and data exchange,in which W5300 TCP/IP hardware protocol stack was used to realize communication between FPGA and the upper machine of the test platform. The result turns out that this test platform works well as expected.
出处
《电子测量技术》
2014年第12期114-119,共6页
Electronic Measurement Technology
