期刊文献+

Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET using trench-based structure

Performance enhancement of c-CESL-strained 95-nm-gate NMOSFET using trench-based structure
原文传递
导出
摘要 A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer(CESL), whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a 2:5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from 333 into 256 MPa, which leads to a significant improvement of the device's I–V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology. A stress modulation technology using a trench-based structure for strained NMOSFET is reported in this paper. With this technology, NMOSFET can be improved by a compressive contact etch stop layer(CESL), whereas the traditional CESL-strained NMOSFET requires a tensile one. To confirm this idea, a 95-nm-gate device with a 2:5 GPa strained CESL is simulated to investigate the effects of the trench-based structure on channel stress. It is demonstrated that the average longitudinal channel stress is transformed from 333 into 256 MPa, which leads to a significant improvement of the device's I–V performance. For strained CMOS, this approach provides a potential alternative besides dual stress liner technology.
出处 《Journal of Semiconductors》 EI CAS CSCD 2015年第1期101-104,共4页 半导体学报(英文版)
基金 Project supported by the Innovative Fund of State Key Laboratory of Electronic Thin Films and Integrated Devices(No.CXJJ201103) the Fund of Analog Integrated Circuit Key Laboratory(No.9140C090301120C09035) the Scientific Research Project of Land and Resources Department of Sichuan Province(No.KJ-2013-12 2200199)
关键词 CESL trench strained NMOSFET SiN CESL trench strained NMOSFET SiN
  • 相关文献

参考文献11

  • 1Khakifirooz A, Cheng K, Loubet N, et al. Hole transport in strained and relaxed SiGe channel extremely thin SOI MOSFETs. IEEE Electron Device Lett, 2013, 34(11): 1358.
  • 2Sun S, Yuan J S, Shen Z J, et al. Performance of trench power MOSFET with strained Si/SiGe multilayer channel. IEEE Trans Electron Devices, 2011, 58(5): 1517.
  • 3Liang Renrong, Zhang Kan, Yang Zongren, et al. Fabrication and characterization of strained Si material using SiGe virtual sub- strate for high mobility devices. Chinese Journal of Semiconduc- tors, 2007, 28(10): 1518.
  • 4Lin C T, Fang Y K, Yeh W K, et al. Impacts of notched-gate struc- ture on contact etch stop layer (CESL) stressed 90-nm nMOS- FET. IEEE Electron Device Lett, 2007, 28(5): 376.
  • 5Orain S, Fiori V, Villanueva D, et al. Method for managing the stress due to the strained nitride capping layer in MOS transistors. IEEE Trans Electron Devices, 2007, 54(4): 814.
  • 6Yang H S, Malik R, Narasimha S, et al. Dual stress liner for high performance sub-45 nm gate length SOl CMOS manufactur- ing. IEEE International Electron Devices Meeting (IEDM), 2004: 1075.
  • 7Uejima K, Nakamura H, Fukase T, et al. Highly efficient stress transfer techniques in dual stress liner CMOS integration. Sym- posium on VLSI Technology, 2007:220.
  • 8Mayuzumi S, Yamakawa S, Tateshita Y, et al. High-pertbrmance metal/high-k n- and p-MOSFETs with top-cut dual stress lin- ers using gate-last damascene process on (100) substrates. IEEE Trans Electron Devices, 2009, 56(4): 620.
  • 9Greene B J, Strane J, Belyansky M, et al. Extending dual stress liner process to high performance 32 nm node SO1 CMOS man- ufacturing. IEEE International SO1 Conference, 2008:17.
  • 10Luo Q, Liu B, Yu Q, et al. Stress management for CESL based strained PMOSFET using trench structure. IEEE 1 lth Interna- tional Conference on Solid-State and Integrated Circuit Technol- ogy (ICSICT), 2012:1.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部