摘要
This paper describes a 65 nm 16-bit parallel transceiver IP macro, whose rate is 3 Gb/s with a 5 p F load including the HBM 2000 V ESD protection. Equalizers and clock data recovery modules, CRC checkers and8 b/10 b encoders are not added in the design for reducing the latency, and the whole latency is 7 ns without cables.Since the transceiver has many robust features including a process, voltage and temperature independent phaselocked loop with calibrations, the low skew differential clock tree, and a stable current mode driver with common mode feedback, the transceiver can work properly at different process corners and extreme temperatures, and also can tolerate 20% power supply variations. The transceiver can be applied for the interface of sub-100 nm high performance processors, which require low latency and high stability. The transceiver shows a bitter error ratio of less than 10^-15 at 3 Gbps.
This paper describes a 65 nm 16-bit parallel transceiver IP macro, whose rate is 3 Gb/s with a 5 p F load including the HBM 2000 V ESD protection. Equalizers and clock data recovery modules, CRC checkers and8 b/10 b encoders are not added in the design for reducing the latency, and the whole latency is 7 ns without cables.Since the transceiver has many robust features including a process, voltage and temperature independent phaselocked loop with calibrations, the low skew differential clock tree, and a stable current mode driver with common mode feedback, the transceiver can work properly at different process corners and extreme temperatures, and also can tolerate 20% power supply variations. The transceiver can be applied for the interface of sub-100 nm high performance processors, which require low latency and high stability. The transceiver shows a bitter error ratio of less than 10^-15 at 3 Gbps.
基金
Project supported by the National High Technology Research and Development Program of China(No.2011AA010403)
the National Natural Science Foundation of China(No.61474134)
