摘要
通过对正余弦函数实现算法的研究,在传统CORDIC算法的基础上,提出了一种分层次超前进位加法器,并以此为基本单元迭代完成了正余弦函数计算算法的设计。该算法采用TSMC 65nm gpg工艺,在Synopsys/syn10.03环境中综合实现,通过NC-SIM仿真和流片验证,加法器运算时间由1.8ns减少到0.42ns,整个系统运算吞吐量也相应提高了3倍。
On the basis of traditional CORDIC algorithms, a hierarchical carry look-ahead adder was proposed through the study of algorithms implements of the cosine function, and the algorithms design of the cosine function was implemented by iterations as the basic unit of hierarchical carry look-ahead adder. The algorithm was implemented in TSMC 65 nm gpg technology, and was synthesized in Synopsys/synl0.03 environment. By NC SIM simulation and silicon taping out, the computation time of the adder was reduced from 1.8 ns to 0.42 ns, and the throughput of the system was increased three times correspondingly.
出处
《微电子学》
CAS
CSCD
北大核心
2014年第6期833-836,841,共5页
Microelectronics
基金
江苏省333工程科研项目资助(BRA2011115)
