FPGA数据总线宽度不相等的双口RAM的设计

Design of Dual Port RAM about Different Data Bus Width Based on FPGA

目前双口RAM两个端口的数据总线宽度相等,而实际应用中,存在着双口RAM两个端口连接的系统的数据总线宽度不相等的问题,为此提出两个端口数据总线宽度不同的双口RAM的FPGA设计方法,双口RAM内部存储器的个数根据2个数据总线宽度比进行设计,在数据总线宽度小的端口设计逻辑控制电路,满足该端口分时进行的读写操作;根据这种双口RAM的读写操作特点,两个端口同时对某一存储单元进行读写操作时,设计存储单元数据总线宽度小的端口具有读写优先权的仲裁机制。对应用Verilog HDL设计的这种双口RAM进行了综合仿真测试,结果表明该双口RAM读写操作正确,具有可行性和实用性。

Currently the dual port RAM data bus width equals to the ports, but in practical application, there is a problem about the data buses of a dual port RAM＇ s two ports connected to the system are not equal. Therefore put forward a new method using FPGA which is the data bus number of each port is not equal to each other, the number of daul port RAM internal storage based on the width ratio, in the width smaller port design logic control circuit, meet the ports time-sharing operations of reading and writing. According to the characteristics of the dual port RAM read and write operations, when two ports simultaneously read and write to a memory cell, the width smaller ports have priority to read and write. A comprehensive simulation test on this dual port RAM in Verilog HDL design, the results show that the dual port RAM read and write proper operation, feasibility and practicality.