定长LT码的FPGA设计与实现

FPGA design and implementation of fixed length LT code

LT码是一类典型的喷泉码,具有较强的纠错纠删能力,在网络通信和深空通信中有较大的应用潜力。在介绍LT码基本思想和编译码原理基础上,设计了定长LT码编码器和译码器的FPGA实现结构,对其所需实现资源进行了深入分析,验证了LT码硬件实现的可行性,同时对所设计的LT编码及译码过程进行了Matlab仿真实验,实验证明丢包率不同对LT码的性能影响不大,而度分布则产生了很大的性能差别。

LT code is a typical fountain code that has high ability of error-correcting and erase-correcting and has application potential in network and deep space communication. Based on the introduction of basic concept and principle of coding and decoding, FPGA implementation structure of encoder and decoder for fixed length LT code is designed. The resource required for implementing LT eodec is analyzed deeply and its feasibility is proved. At the same time, Matlab simulation experiment of the process of LT eneoder and decoder is conducted, which proves that the differences of packet loss ratio don＇ t have too much effect on LT code, but degree distribution brings about great performance difference.