电路逻辑单元单粒子效应敏感性研究

Study on Sensitivity of Logic Unit in the Circuit for Single Event Effects

介绍了时序逻辑单元和组合逻辑单元发生单粒子效应的机理,以反熔丝型FPGA芯片ActelA54SX32A为实验对象,设计了3种典型的链电路系统。在中国原子能科学院HI-13串列静电加速器上采用Br离子对电路进行辐照实验,在频率为20 MHz的条件下,3个链电路的翻转截面分别约为3.268×10-3 cm2,7.449×10-4 cm2和3.988×10-4 cm2。实验结果验证了在0.22μm工艺条件下,时序逻辑单元比组合逻辑单元更加敏感,并且在包含两者的电路中,组合逻辑单元会屏蔽部分单粒子效应。最后,针对电路中不同逻辑单元,给出了两种加固方法。

The mechanism of single event effects in temporal logic unit and combinational logic unit is described. Taking the anti-fuse FPGA chip ActelA54SX32A as the experimental object, we designed three typical chain circuitry. Circuits are irradiated at frequency of 20 MHz by Br ions HI-13 Tandem Accelerator from China Institute of Atomic Energy, the cross section of the chain circuitry are 3. 268 × 10-3 cm2 , 7. 449 × 10-4 cm2 , and 3. 988 × 10-4 cm2, respectively. The experimental results show that under 0.22 μm process condition, the temporal logic unit is more sensitive than the combinational logic unit, but the latter would shield part of single event effects. Finally, two reinforcement methods are introduced according to the different logical units.