摘要
高速FIR滤波器的8路多相直接分解实现结构的工作频率是单路串行实现结构的1/8,计算复杂度是单路串行实现结构的8倍。针对高速FIR滤波器的8路多相直接分解实现结构计算复杂度大这一问题,对FIR滤波器的多相并行实现结构进行了详细推导,提出了FIR滤波器的8路多相27子滤波器实现结构,提出的FIR滤波器的8路多相27子滤波器实现结构的计算复杂度是单路串行实现结构的3.375倍。FPGA实验验证了提出的FIR滤波器的8路多相27子滤波器实现结构的优越性。
Compared with the one-way serial FIR filter,the operational frequency of implementation structure of direct 8-channel polyphase decomposition of high-speed FIR filter is decreased to 1/8,and eight times as much as its computational complexity.According to the problem that the implementation structure of direct 8-channel polyphase decomposition of high-speed FIR filter has enormous computational complexity,the detailed analysis of the parallel implementation structure of polyphase filter is derived,and the implementation structure of 8-channel polyphase FIR filter with 27 subfilters is proposed.The proposed implementation structure of 8-channel polyphase FIR filter with 27 subfilters has 3-375 times the computational complexity of that of one-way serial FIR filter.The FPGA implementation experiment proves the superiority of the proposed implementation structure of 8-channel polyphase FIR filter with 27 subfilters.
出处
《无线电工程》
2015年第2期22-25,63,共5页
Radio Engineering
基金
国家高新技术研究发展计划("863"计划)资助项目(2011BAH05B01)
关键词
FIR滤波器
多相分解
子滤波器
实现结构
FIR filter
polyphase decomposition
subfilter
implementation structure