C程序映射到FPGA的寄存器快速评估技术

Rapid Register Estimation Technique for Mapping C-applications onto FPGAs

在基于FPGA的软硬件协同设计中,对硬件面积和延迟时间进行快速准确地评估是快速生成片上异构多处理器系统的关键步骤.使用传统的逻辑综合工具将会耗费大量的时间才能获得面积-时间的度量值,导致在软硬件协同设计流程中,抑制了设计空间的有效探索.本文关注将C程序映射到FPGA,对寄存器数量进行快速和准确的评估.提出的技术以高级综合工具Leg Up和底层虚拟机LLVM为基础,利用信号位宽优化信息、特殊指令信息以及编码方式对寄存器进行评估.实验结果表明,该技术能够对CHStone基准测试程序进行寄存器数量的评估;以Altera CycloneⅡ和StratixⅣFPGA为平台,实验结果的误差分别只有13.75%和10.48%,与使用Quartus工具的逻辑综合运行时间相比,能够实现84倍的加速.

Rapid area-time estimation is an essential step for hardware-software co-design of FPGA-based implementations. However, acquisition of area-time measures using conventional logic synthesis tools are time consuming, and prohibit efficient design space ex- ploration in the co-design flow. This paper focuses on the fast and accurate registers estimation technique for mapping C-based applica- tions onto FPGA. The technique relies on LegUp high-level synthesis tool and Low Level Virtual Machine, it uses the optimized bit- width of signal,special instruction and encoding scheme to estimate registers. Experimental results show that the proposed technique is able to estimate the number of registers required for all the C-based applications in CHStone benchmark suite with an average estima- tion error of only 13.75% and 10. 48% for Altera Cyclone II and Stratix IV FPGA respectively. The proposed technique achieves 84 times faster when compared to logic synthesis run-time using Altera＇s Quartus tool.