容错处理器阵列的并行重构及VHDL实现

Parallel Reconfiguration for Processor Arrays with Faults Utilizing VHDL

网格连接的处理器阵列是一种应用广泛的高性能体系结构,而容错处理器阵列的重构技术是近年来的研究热点之一.现有的研究多数集中在串行重构算法上,忽视了该结构重构时内在的可并行性.本文根据阵列结构的特点设计了一种基于VHDL语言的重构算法,该算法从第一行的各个无故障处理器单元同时向下选路,具有潜在的并行性,.实验结果表明,与现有的串行算法相比,本文提出的并行算法同样能够生成最大规模的目标阵列并且当物理阵列大小为48×48,本文提出的并行算法加速重构将近20倍.

Mesh-connected processor array is an extensive high-performance architecture used in parallel processing. The reconfigura- tion techniques on fault-tolerant processor array are one of most popular issues in recent year. The existing studies are focused on serial reconfiguration algorithm but few works are reported on parallel reconfiguration. In this paper, we propose a reconfiguration algorithm based on VHDL which has advantage of potential concurrency. One processor is regarded as the basic component according to the fea- ture of processor array in the proposed algorithm which generates the logical columns in parallel by starting from the fault-free proces- sors on first row. Experimental results show the proposed algorithm accelerates the reconfiguration nearly by 20 times on 48 ×48 arrays with same size of target array as one generated by traditional serial algorithm cited in this paper.