基于Vivado HLS的FPGA开发与应用研究

Development and application of FPGA based on Vivado HLS

为在硬件中更快速地实现数字信号处理或图像处理算法,可使用Vivado HLS工具与Zynq系列的全可编程SoC进行FPGA的设计与开发.开发者能够借助它们直接使用C或C++语言进行FPGA的开发,相对于Verilog或VHDL设计而言,开发周期短、成本低。本文详细介绍了Vivado HLS工具的特点与应用等内容,并以"图像色调分离"和"循环编码器"两种不同类型的实例,描述了该工具的使用方法与设计技巧.

In order to more rapid implementation of digital signal processing and image processing algorithm in hardware design.Vivado High-Level Synthesis（HLS）design tools can be used in the design and development of Zynq All programmable with FPGA.HLS can transform a C or C＋ ＋ design specification into a Register Transfer Level implementation which can be synthesized into a Xilinx FPGA.Compared with Veirlog or VHDL design,this tool will reduce development cycles and costs of FPGA.This paper describes the characteristics and applications of HLS in detail.With the examples of image posterization and loop encoder,we can learn the design method and skills.