星载伪码测距系统精确同步及FPGA实现

Design and FPGA realization of precise synchronization in spaceborne pseudo-code ranging system

针对星载伪码测距系统中伪码同步的实现问题,给出了一种适宜在FPGA中实现的结构。系统采用归一化超前减滞后功率鉴相器以及二阶环路滤波的架构,对非相干延迟锁定环路进行理论分析和仿真,并给出了FPGA中实现资源统计。仿真结果表明,该方法具有很高的伪码跟踪精度,满足星载伪码测距的要求。

Aiming at the paper presents a suitable normalized advance minus problem of pseudo-code synchronization in spaceborne ranging system, this architecture implemented in the FPGA. The system uses the architecture of lagging power phase detector and second-order loop filter for non-coherent delay locked loop theoretical analysis and simulation, and it gives out the FPGA resource statistics. The simulation results show that this method has high pseudo-code tracking accuracy, which meets the requirements of spaceborne PN ranging.