基于SystemVerilog可重用测试平台的实现

The implementation of a reusable testbench based on System Verilog

对于中小型设计,传统的验证效率低、可重用性差,而基于方法学的高级验证测试平台搭建较繁琐,验证流程不太灵活。以ARINC429收发器IP核为验证对象,采用System Verilog语言,通过层次化设计,改善工程组织架构,运用虚接口与回调等关键技术,实现了一种可重用测试平台。将不同的测试案例在测试平台上运行,结合断言与覆盖率驱动等验证技术完成了对ARINC429收发器IP核的功能验证,代码覆盖率和功能覆盖率均达到100%。实践表明,该测试平台具有良好的可重用性、易操作性,验证效率较高。

For small and medium-sized design, the traditional verification has low efficiency and poor reusability, while the advanced methodology-based verification is a bit complicated to build testbench, and the verification flow is not very flexible. The implementation of a reusable testbench is presented in this paper. The testbench is used to verify the IP core of ARINCg29 transceiver, and it is implemented by employing the SystemVerilog language, designing the hierarchical structure, improving the ar- chitecture of project, and adopting key technology such as virtual interface and callback. With the assertions and coverage-drlven verification technology, the functional verification is completed by running different testcases on this testbench, both code coverage and functional coverage are 100%. The practice shows that the testbench is reusable, easy to operate, and efficient.