一款高性能时钟驱动器电路的设计

Design of a High-performance Clock Buffer

时钟器件芯片可以实现通信网定时同步、时钟产生、时钟恢复和抖动滤除、频率合成和转换、时钟分发和驱动等功能。在系统设计中,选用好的时钟驱动芯片,可以省去系统时钟树设计,既节省空间,又提高系统性能。介绍一款高性能时钟驱动器的集成电路设计方法,主要性能要求有:低传播延时、低输出偏斜、低输出抖动、抗电磁干扰能力、抗ESD能力,一一详述了达到各项要求的设计。

The article relates to a method for designing a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal to the output clocks. It can operate at 0 MHz to 200 MHz and the output enable control that can drive outputs low when OE is low. It is specifically designed for use with PCI-X applications. It operates at 3.3 V and 2.5 V and is therefor compliant to the 3.3 V PCI-X specifications.