适用于10Gbps以太网物理层收发器的变速箱电路设计

An Efficient Design Methodology for Gearbox Circuits in 10 Gbps Ethernet Transceiver

提出一种新的变速箱电路的设计方法。在不降低变速箱两边数据传输比特率的前提下,使用电路中固定时钟源产生两个基础时钟,再通过这两个基础时钟组合成变速箱的输入时钟和输出时钟。其中组合后的时钟周期是不均等的,但是其平均周期值是定值,确保变速箱两边的传输比特率相等,从而解决在传输过程中数据的重复或者丢失问题,实现两边不同数据位宽的正确转换,可以广泛用于10 Gbps以太网的物理层收发器中的变速箱电路。

An efficient gearbox which adjusts the data width between Serdes（serilizer and deserializer）and PCS（physical coding sub-layer）in a 10 G Base-R transceiver which lowers the complexity of Serdes design without downgrading the effective data rate, is presented. The gearbox consists of one clock generation unit（CGU）and one data shifting unit（DSU）. The clock generation unit generates two nonuniformed but synchronous clocks with average frequency equal to the designated clock frequency by utilizing the clock source from the Serdes. The data shifting unit utilizes the generated clocks from the CGU to shift in and shift out the data from the PCS to Serdes, or from Serdes to the PCS.