摘要
本文首先讨论了一种适用于高速场合的RS编码器的算法与结构—它由1+r个脉动单元组成,其中r为校验位的数目。这种编码算法是基于码生成元矩阵的柯西表达,编码器中没有限制其开关速度的全局时钟,故可在高速场合中得到应用,然后给出了一种应用于该编码器的改进方案:该方案消除了柯西单元中的除法器,并且还没有了求逆运算,故降低了编码器的复杂度,可有效地加速编码器的数据吞吐率,从而使其更适用于极高速场合。
Firstly, algorithm and structure for RS encoder suiting high application situation were discussed. The encoder consists of r+1 systolic cells, where r is the checking bit numbers. The algorithm of encoder was based on Cauchy representation of generator matrix of the code. There is no global clock in the encoder to pose restrictions on the achievable switching speed of the encoder and so it is suitable for the high-speed applications. Secondly, a modified scheme for the systolic RS encoder was presented: the scheme erases the dividers in the Cauchy cells and the inversion, reduces the complexity of the encoder. So it can boost the throughout of the encoder effectively and is suitable for the very high-speed applications.
出处
《通信学报》
EI
CSCD
北大核心
2002年第7期76-82,共7页
Journal on Communications
基金
国家"863"高技术项目(863-2-7-4-6)