基于FPGA的改进型全数字锁相环的设计

Design of an improved all-digital phase-locked loop based on FPGA

针对脉冲密度调制技术调节谐振逆变器输出功率时系统易失锁的问题,提出了一种改进型全数字锁相环,详细分析了这种全数字锁相环的工作原理。利用通用的现场可编程门阵列器件（FPGA）实现改进型全数字锁相环的片上系统设计。最后通过仿真和实验证明,对于不同频率的跟踪信号,当起始相位误差约为最大值180°时经过10-11个输入信号周期系统就可以快速而准确的锁定。而当负载电流降至很小的值时改进锁相环的采样保持电路能够保证逆变器工作在谐振频率点附近,从而避免失锁。

When the pulse density modulation technique is used to regulate the output power of the resonant inverter,the system is easily un-locked. In order to solve this problem, an improved all-digital phase-locked loop was designed, and its working principle was analyzed in detail. The common field-programmable gate arrays（FPGA） was used to achieve the system on chip design of the improved all-digital phase-locked loop. Finally, the simulation and experiment prove that when the initial phase error is approximately the maximum 180°, after 10 to 11 input signal cycles the system can quickly and accurately lock with tracking signals of different frequencies. When the load current drops to a very small value, the operation of sample and hold（S/H） circuit in the improved phase-locked loop ensure that the power inverter operates in the vicinity of the resonant frequency and the un-locked case is avoided.