基于FPGA的五级流水线CPU

Five Stage Pipeline CPU Based on FPGA

基于FPGA平台设计并实现了一种五级流水线CPU.它参考MIPS机将指令的执行过程进行抽象,把指令分成取值、译码、执行、访存、写回五级流水处理.首先设计系统级的结构,决定CPU的结构和指令系统.其次对整体结构进行分解,确定模块与模块之间的信号连接,采用VHDL实现CPU.最后通过Debug-controller调试软件对五级流水线CPU进行调试.结果表明了所设计的流水线CPU的有效性.

A five stage pipeline CPU was designed and implemented on FPGA. Referring to MIPS machine and analyzing the process of each instruction, the process was divided into five stages which are IF, ID, EXE, MEM, and WB. The design of system-level structure was placed in the first position in order to determine the architecture and the instruction set. The next work was decomposing the integrated architecture and determining the signal connection between the module and the module. The CPU was implemented with VHDL. Finally, the five stage CPU was debugged by debugging software which is called Debug-controller. The result shows that the pipeline CPU is effective.