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基于FPGA和TDC-GP2的钟差测量系统设计 被引量:7

Design of clock difference measurement system based on FPGA and TDC-GP2
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摘要 在航天试验靶场,频标设备的频率准确度直接决定了测控设备测量数据的质量,而频率准确度的测量依赖标准频率与本地频率的钟差测量,目前在各测控站点一般采用高精度计数器来实现,但由于计数器输出的钟差测量结果只能在本地显示而不能进行远程传输,导致总体人员不能在时钟主站有效对各测控站点的守时情况进行实时监测和辅助判决,易出现调钟错误的问题。提出了一种基于FPGA和TDC-GP2的钟差测试系统设计方案,可对本地的钟差进行测量,测量精度高达100ps,并通过试验任务IP网进行上报,达到对守时结果远程监测和辅助判决的目的。 In the aerospace test range,the accuracy of the frequency standard equipment decides directly the data performance of measurement and control equipment,but it is dependent on the clock difference measurement of the standard frequency and the local frequency.At present,it is realized by high-precision counter,but the measurement result can only be displayed in the local and not be transferred over long distance,which can not effectively monitor and judge to keep watch time for system person in the master station and the regulation clock error easily occur.A project of clock difference measurement is proposed based on FPGA and TDC-GP2,which complete the measure of clock difference in the local.The time measurement precision can achieve 100 ps,it will attain the purpose of monitoring and judging the keep watch time result by using test task IP network to report the measurement data.
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出处 《国外电子测量技术》 2015年第1期63-68,共6页 Foreign Electronic Measurement Technology
关键词 频标设备 FPGA TDC-GP2 钟差测量 frequency standard equipment FPGA TDC-GP2 clock difference measurement
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