摘要
This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process.Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.
This paper presents an embedded SRAM design for write buffer applications in flash memories. The write buffer is imple- mented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135 μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process. Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.
基金
supported by the MOST(Grant Nos.2010CB934200 and 2011CBA00600)
the National Natural Science Foundation of China(Grant Nos.61176073 and 61221004)
