摘要
针对嵌入式处理器对面积要求极为苛刻的特点,提出了一种改进的基于Goldschmidt算法的双精度浮点除法器。改进的除法算法的计算过程分为两个阶段,第一阶段采用线性minimax多项式逼近算法得到一个具有15-bit精度的除数倒数的估计值。相比于minimax二次多项式逼近,一次多项式逼近会获得一个更小的查找表(LUT)以及在部分积累加过程中获得更少的计算量。在第二阶段,采用基于硬件复用的方法实现两次Goldschmidt迭代,使得两次Goldschmidt迭代仅仅使用一个乘法器和一个求补单元。最后,该设计采用Verilog HDL进行编码,并基于FPGA进行实现。通过与其他算法进行比较得知,改进的Goldschmidt除法器在性能不降低的情况下有较小的面积开销,满足嵌入式处理器的需求。
An improved Goldschmidt double-precision floating-point divider is presented to meet the demand of the embedded devices which have a very high requirement for area cost. Two computation stages are employed to carry out this division algorithm. Firstly, a linear-degree minimax polynomial approximation is used to obtain a 15-bit precision estimate of the reciprocal. Then two iterations employing Goldschmidt algorithm specially designed for hardware reuse is performed to gain the final accurate result of division. Finally, the design was implemented by Verilog HDL and prototyped in FPGA. Comparisons with other work show that proposed divider has lower area cost with no performance degradation which meets the requirement of embedded microprocessor.
出处
《电子设计工程》
2015年第3期50-53,共4页
Electronic Design Engineering
