1.5 GHz Serdes低抖动锁相环的设计

Design of 1.5GHz Serdes low jitter PLL

设计并实现了一种应用于1.5GHz Serdes高速接口系统的低抖动锁相环。出于应用考虑,设计的重点是降低抖动,根据锁相环的系统特点、噪声特性以及物理实现时的种种外部干扰因素的影响,分别提出了系统级设计、电路设计以及版图设计上的减小噪声、降低抖动的方法。电荷泵锁相环采用0.18μm 1P4M互补金属氧化物半导体(CMOS)混合信号工艺制造,芯片面积为700μm×320μm。仿真结果表明,电路中心频率为1.5GHz,锁定时间小于5μs,偏离中心频率1MHz处的相位噪声为-95.39dBc/Hz,RMS jitter为3.6ps,总功耗为6mW。

A low jitter charge pump phase locked loop(CP PLL)is designed and implemented for high speed Serdes interface system.The main purpose of this paper is to reduce the jitter of PLL.According to the characteristics of PLL system model,linear noise model and other possibilities of increasing phase noise in physical design,a series of methods are proposed system-level design,circuit design and layout design to reduce noise and reduce jitter.Fabricated in 0.18μm CMOS 1P4 M mixed signal technology,the area of CP PLL on a chip is 700μm×320μm.In the simulations,the center frequency of circuit is 1.5GHz,the locking time is less than 5μs,the phase noise is-95.39dBc/Hz@1MHz with 6mW power consumption,and the RMS jitter is 3.6ps.